In recent years, great advances have been made in increasing the power efficiency of analogue-to-digital converters. Currently, the most efficient implementations are based on a successive approximation register (SAR) architecture.
In a typical successive approximation register analogue-to-digital conversion (SAR ADC) architecture the input Vin is compared against a digital-to-analogue converter (DAC) output VA using a comparator in several cycles. The input first goes through a sample and hold block. The SAR search logic block executes a search algorithm, which typically performs a binary search. In the first cycle the input is compared against the middle of the ADC range. From the comparator output the most significant bit (MSB) can be determined. In the next cycle MSB-1 is determined. A conversion to n bits requires n cycles. The SAR ADC is low in cost and consumes low operating power. The excellent power efficiency of the SAR converter can be attributed both to the inherent efficiency of the binary search algorithm and the simplicity of the required hardware.
A conventional SAR ADC scheme is depicted in FIG. 1. A sample and hold circuit is included, as well as a comparator, a DAC and a digital SAR controller. The analogue signal Vin enters the sample and hold (S/H) circuit where the signal simply is sampled and held to provide a buffer for the A/D converter. Vin is compared in the comparator to comparator reference voltage Vref. The digital comparison result goes to the SAR controller block comprising the search logic. The controller block adjusts the digital control signals in order to narrow the compared voltages. An adjusted digital signal is outputted to a digital-to-analogue converter (DAC). This signal is converted to an adjusted Vref, which is compared to Vin in the comparator. A common implementation of the DAC uses an array of capacitors which are controlled by the SAR controller block.
Digital calibration is applied to measure and compensate for analogue imperfections in these SAR A/D converters. The analogue imperfections to be mitigated through digital calibration are typically located in the DAC (in order to achieve linearity) and the comparator (to compensate offset).
Digital calibration of comparator offset can be achieved by sampling a zero input voltage, which is then applied to the comparator input. Based on the comparator outputs, the comparator offset can then be inferred and minimized. The reference voltage for the calibration is simply the zero input voltage, which does not require dedicated circuitry to generate. This is illustrated for a differential implementation in FIG. 2, where a DAC implementation with an array of capacitors as previously mentioned can be seen.
Digital calibration of the DAC linearity has been applied in the art to a number of different DAC implementations in order to compensate for various non-idealities, such as capacitor mismatch, parasitic capacitance, etc. All of these calibration steps share the same three fundamental steps. First, the ADC samples a zero input voltage, such that the comparator input is also zero. Next, the DAC is switched such that any DAC error is generated at the comparator input. Finally, the comparator output is observed to determine the polarity of the DAC error. Again, the reference voltage for this calibration is simply a zero input voltage, which again does not require dedicated circuitry to generate. This is illustrated for the case of MSB mismatch calibration in FIG. 3.
Recent implementations of SAR ADCs have departed from the conventional implementation of FIG. 1, usually with the goal of further improving power efficiency. One option is to use a specific, different comparator in each step of the binary search, and a differential DAC that changes its output common mode as well as its differential mode, as shown in FIG. 4.
At the start of a conversion, the input voltage is sampled and the first comparator is activated. If this comparator decides its input is positive, the MSB capacitance of the DAC connected to the positive comparator input is switched from the reference to ground, reducing the differential comparator input by VstepMSB and lowering the comparator input common-mode by VstepMSB/2, as shown on the right in FIG. 4. If, on the other hand, the comparator decides the input is negative, the other MSB capacitance is switched, lowering instead node comp−. As was the case for a positive comparator output, the common-mode of the comparator input is lowered by VstepMSB/2. The common-mode of the comp+ and comp− signals is thus independent of the comparator decisions. An appropriate time after the first comparator decision (whereby ‘appropriate’ means allowing enough time for the DAC output to settle), the second comparator is activated and the process is repeated for all lower order bits.
One potential advantage of always switching the DAC from reference to ground, and never from ground to reference, is that all DAC settling occurs through an NMOS rather than PMOS switch, which benefits settling speed. One potential disadvantage of this arrangement is the changing common-mode level of the comparator input, which can result in comparator errors due to common-mode dependent comparator offset. This drawback can be solved by implementing a dedicated comparator for each step of the binary search. Indeed, since each comparator is only activated in a specific cycle and the common-mode comparator input in a specific cycle is well known and independent of the preceding comparator decisions, each comparator is only ever activated at a specific common-mode input. By calibrating each comparator offset at its specific common-mode input voltage level, the problem of common-mode dependent comparator offset can thus be avoided.
A straightforward way to calibrate such comparator offsets is to sample a zero differential input voltage of the correct common-mode, which is then applied to the comparator in question. By observing this comparator's output, offset can be inferred and minimized. However, in this approach, each comparator in the converter requires a specific calibration reference: a zero differential input voltage of a specific common-mode voltage. Indeed, if the nominal ADC operates with a common-mode input voltage of Vcm, zero differential inputs at Vcm (first comparator), Vcm−VstepMSB/2 (second comparator), Vcm−3*VstepMSB/4 (third comparator) etc. are required. To generate these signals, a specific calibration DAC would be required, at the cost of valuable circuit area, design time and power consumption. FIG. 5 provides an illustration of this drawback.
In the paper “A Self-Testing and Calibration Method for Embedded Successive Approximation Register ADC” (Xuan-Lun Huang et al., Asia and South-Pacific Design Automation Conference (ASP-DAC) 2011, January 2011, pp. 713-718) a low cost design-for-test technique is proposed which tests a SAR ADC by characterizing its DAC capacitor array. Direct control of the DAC capacitor array is proposed to generate the required DAC major carrier transitions and measure them by an integrated ADC comprising the comparator of the SAR ADC and an additional design-for-test DAC. Then a fully-digital missing code calibration technique is developed that utilizes the testing scheme to collect calibration information. More particularly, the main SAR DAC capacitor array is switched to generate an error voltage and the additional test DAC is used to quantize the error. The proposed arrangement is not suited for generating calibration references, since the DAC itself is assumed to be inaccurate.
Application US2010/214140 relates to digital trimming of SAR ADCs. A SAR ADC is provided that performs error correction in order to reduce cost. This is accomplished by adding correction capacitors that can correct for DAC non-linearity. It is not specified how said DAC non-linearity is measured. The proposed arrangement is not suited for generating calibration references since the DAC itself is assumed to be inaccurate.
In the paper “A 480 mW 2.6 GS/s 10 b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS” (Kostas Doris et al., IEEE Journal of Solid-State Circuits vol. 46, no. 12, December 2011), calibration is used to compensate inter-channel gain and offset mismatch as well as DAC non-linearity. Off-chip references are used for channel gain and offset calibration, the DAC linearity is measured by comparing each consecutive MSB to the sum of its LSBs. Again the proposed arrangement is not suited for generating calibration references since the DAC itself is assumed to be inaccurate.
Hence, it is desirable to find a way to overcome the need to use dedicated equipment to generate specific calibration reference signals.